module ram_dp_128d_11w_wrapper(
    input                   clka ,
    input                   clkb ,
    input   [11:0]          ram_dp_cfg_register ,

    input                   wea_n ,
    input   [6:0]           addra ,
    input   [10:0]          dina ,
    output  [10:0]          douta ,
    input                   web_n ,
    input   [6:0]           addrb ,
    input   [10:0]          dinb ,
    output  [10:0]          doutb
) ;

    ram_dp_d128_w11 U1_ram_dp_128d_11w ( 
        .CENYA              (),
        .WENYA              (),
        .AYA                (),
        .CENYB              (),
        .WENYB              (),
        .AYB                (),
        .QA                 (douta),
        .QB                 (doutb),
        .SOA                (),
        .SOB                (),

        .CLKA               (clka),
        .CENA               (1'b0),
        .WENA               (wea_n),
        .AA                 (addra),
        .DA                 (dina),
        .CLKB               (clkb),
        .CENB               (1'b0),
        .WENB               (web_n),
        .AB                 (addrb),
        .DB                 (dinb),

        .EMAA(ram_dp_cfg_register[11:9]),
        .EMAWA(ram_dp_cfg_register[8:7]),
        .EMASA(ram_dp_cfg_register[6]),
        .EMAB(ram_dp_cfg_register[5:3]),
        .EMAWB(ram_dp_cfg_register[2:1]),
        .EMASB(ram_dp_cfg_register[0]),

        .TENA(1'b1),
        .TCENA(1'b1),
        .TWENA(1'b1),
        .TAA(7'b0),
        .TDA(11'b0),
        .TENB(1'b1),
        .TCENB(1'b1),
        .TWENB(1'b1),
        .TAB(7'b0),
        .TDB(11'b0),
        .RET1N(1'b1),
        .SIA(2'b0),
        .SEA(1'b0),
        .DFTRAMBYP(1'b0),
        .SIB(2'b0),
        .SEB(1'b0),
        .COLLDISN(1'b1) 
    );

endmodule
